usb copyright ? 2006 by silicon laboratories 1.4.2006 uart1 64 kb flash 256 byte sram por sfr bus 8 0 5 1 c o r e reset rst/c2ck external oscillator circuit debug hw brown- out p 0 d r v 4 kb xram xtal1 xtal2 p0.0 p0.1 p0.2/xtal1 p0.3/xtal2 p0.4 p0.5 p0.6/cnvstr p0.7/vref spi regin c r o s s b a r p 1 d r v p1.0 p1.1 p1.2 p1.3 p1.4 p1.5/ale p1.6/rd p1.7/wr port 0 latch smbus timer 0,1,2,3 / rtc uart0 system clock p 2 d r v p 3 d r v p2.0/a0 p2.1/a1 p2.2/a2 p2.3/a3 p2.4/a4 p2.5/a5 p2.6/a6 p2.7/a7 c2d p1 latch pca/ wdt usb controller usb transceiver analog/digital power voltage regulator 5.0v 1 kb usb sram vbus d+ d- 12 mhz internal oscillator gnd vdd in out enable x4 2 usb clock 2 1,2,3,4 clock recovery p3.0/a8/c2d p3.1/a9 p3.2/a10 p3.3/a11 p3.4/a12 p3.5/a13 p3.6/a14 p3.7/a15 external data memory bus 10-bit 200 ksps adc a m u x ain0-ain16 vref vdd cp1 + - temp vdd cp0 + - vref vref p 4 d r v p4.0/d0 p4.1/d1 p4.2/d2 p4.3/d3 p4.4/d4 p4.5/d5 p4.6/d6 p4.7/d7 c t l p2 latch a d d r p3 latch p4 latch d a t a C8051F340 usb, 48 mips, 64 kb flash, 10-bit adc, 48-pin mixed-signal mcu analog peripherals 10-bit adc - 1 lsb inl; no missing codes - programmable throughput up to 200 ksps - up to 17 external inputs; programmable as single-ended or differential - built-in temperature sensor (3 c) two comparators internal voltage reference: 2.4 v por/brown-out detector usb function controller - usb specification 2.0 compliant - full-speed (12 mbps) or low-speed (1.5 mbps) operation - integrated clock recovery; no external crystal required for either full- speed or low-speed operation - supports eight flexible endpoints - dedicated 1 kb usb buffer memory - integrated transceiver; no external resistors required on-chip debug - on-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) - provides breakpoints, single stepping - inspect/modify memory, registers, and usb memory - superior performance to emulation systems using ice-chips, target pods, and sockets temperature range: ?40 to +85 c high-speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 48 mips throughput with 48 mhz clock - expanded interrupt handler memory - 4352 bytes data ram (256 + 4 kb) - 64 kb flash; in-system programmable in 512-byte sectors (512 bytes are reserved) - external parallel data memory interface digital peripherals - 40 port i/o; all are 5 v tolerant - hardware smbus? (i 2 c? compatible), spi?, and 2 uart serial ports available concurrently - 4 general-purpose 16-bit counter/timers - programmable 16-bit counter array with 5 capture/compare modules clock sources - internal oscillator: 0.25% accuracy with clock recovery enabled; supports all usb and uart modes - external oscillator: crystal, rc, c, or clock - on-chip clock multiplier: up to 48 mhz voltage regulator - on-chip voltage regulator supports usb bus-powered operation - regulator bypass mode supports usb self-powered operation operating voltage: 2.7 to 5.25 v package - 48-pin tqfp (lead-free package) ordering part number - C8051F340-gq
usb copyright ? 2006 by silicon laboratories 1.4.2006 silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned her ein are trademarks or registered tr ademarks of their respective holders C8051F340 usb, 48 mips, 64 kb flash, 10-bit adc, 48-pin mixed-signal mcu selected electri cal specifications (t a = 0 to +70 c, vreg = 5.0 v unless otherwise specified) parameter conditions min typ max units global characteristics regulator input voltage (regin) 4.0 ? 5.25 v v dd (vreg output) 3.0 3.3 3.6 v v reg bias current v reg enabled ?90? a supply current with cpu and usb active cpu clock = 24 mhz, usb clock = 48 mhz cpu clock = 12 mhz, usb clock = 6 mhz ? 18 9 ? ma ma supply current (suspend mode, oscillator off) v dd monitor enabled; v reg disabled v dd monitor disabled; v reg disabled ? 30 <0.1 ? a a cpu system clock range dc ? 25 mhz internal oscillator & clocks frequency clock recovery enabled clock recovery disabled 11.97 11.82 12.0 12.0 12.03 12.18 mhz mhz usb clock full-speed operation low-speed operation 47.88 5.91 48.0 6.0 48.12 6.09 mhz mhz a/d converter resolution 10 bits integral nonlinearity ? ? 1lsb differential nonlinearity guaranteed monotonic ? ? 1lsb signal-to-noise plus distortion 51 ? ? db throughput rate ? ? 200 ksps input voltage range 0? v ref v comparator response time mode0 (cp+) ? (cp-) = 100 mv ? 0.1 ? s current consumption mode0 ?7.6? a response time mode1 (cp+) ? (cp-) = 100 mv ? 0.18 ? s current consumption mode1 ?3.2? a response time mode2 (cp+) ? (cp-) = 100 mv ? 0.32 ? s current consumption mode2 ?1.3? a response time mode3 (cp+) ? (cp-) = 100 mv ? 1 ? s current consumption mode3 ?0.4? a package information a a1 a2 b d d1 e e e1 - 0.05 0.95 0.17 - - - - - - - 1.00 0.22 9.00 7.00 0.50 9.00 7.00 1.20 0.15 1.05 0.27 - - - - - min (mm) nom (mm) max (mm) e e1 d d1 48 1 a1 e b pin 1 identifier a2 a C8051F340dk development kit
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